Thesis - University Access Only
Master of Science (MS)
Department / School
Most digital systems are constructed using static CMOS logic and edge-triggered flip-flops. Although such techniques were adequate in the past and remain adequate in the future for low performance design, they will become increasingly inefficient for high performance components as the number of gates per cycle increases and clock skew becomes a greater problem. Designers, therefore, need to adopt better circuit techniques that can tolerate reasonable amounts of clock skew without an impact on the cycle time. Transparent latches offer a simple solution to the clock skew problem in static CMOS logic. For high performance designs, especially microprocessors, static CMOS is inadequate to meet timing objectives. Therefore, designers turn to domino circuits that offer greater speed. However, domino-clocking methodologies have even greater overhead that can defeat the speed advantage of the domino gates. This paper examines different types of circuit families. It also presents a technique using skew-tolerant domino circuits. This method controls domino gates with multiple overlapping clock phases, eliminates clock skew from the critical path, hides the overhead, and offers significant performance improvement. This methodology will be verified using an 8-bit adder circuit. The adder is implemented using static, domino, and skew-tolerant domino circuits. The performance of the skew-tolerant domino circuit is significant. This circuit will run at 1.5 GHz!
Library of Congress Subject Headings
Digital integrated circuits -- Design and construction
Number of Pages
South Dakota State University
Ranganna, Vijayalakshmi, "On The Road to a GHz Adder" (2000). Electronic Theses and Dissertations. 774.